1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, particularly, to a semiconductor device comprising an n-type MIS transistor and a p-type MIS transistor differing from the n-type MIS transistor in the gate material and a method of manufacturing the same.
2. Description of the Related Art
With progress in the miniaturization of an MOSFET, the gate oxide film (gate insulating film) is being made thinner and thinner. For example, in an MOSFET having a gate length not greater than 50 nm, required is a very thin gate oxide film having a thickness of about 1 nm. It is difficult to form such a thin gate oxide film because, for example, polycrystalline silicon (polysilicon) used for forming the gate electrode is depleted. If polysilicon is not depleted, it is possible to further decrease the thickness of the gate oxide film to about 0.5 nm. Such being the situation, a MOSFET (a MISFET) having a metal gate electrode structure in which a metal free from the depletion phenomenon is used for forming the gate electrode, attracts attentions.
However, a serious problem is generated as follows in the case of using a single kind of a metal for forming the gate electrode. Specifically, an n-type MISFET and a p-type MISFET are rendered equal to each other in the work function of the gate electrode. As a result, it is impossible to make the n-type MISFET and the p-type MISFET different from each other in the work function of the gate electrode, though the n-type MISFET and the p-type MISFET can be made different from each other in the work function of the gate electrode in the case of using a polysilicon gate. It follows that it is very difficult to make the threshold voltage appropriate. Particularly, in order to achieve a low threshold voltage not higher than 0.5 V, it is desirable to use a material having a work function not higher than 4.6 eV, more preferably not higher than 4.3 eV, for forming the gate electrode of the n-type MISFET, and to use a material having a work function not lower than 4.6 eV, more preferably not lower than 4.9 eV, for forming the gate electrode of the p-type MISFET. Under the circumstances, required is a so-called dual metal gate process in which the gate electrode of the n-type MISFET is formed of a metal material differing from that used for forming the gate electrode of the p-type MISFET.
In the dual metal gate process, it is necessary to form the gate electrodes of the n-type MISFET and the p-type MISFET in different processes. Therefore, a first film of a gate electrode material for one of the n-type MISFET and p-type MISFET, e.g., the n-type MISFET, is formed on the entire surface including the region in which both n-type MISFET and p-type MISFET are formed. Then, the first gate electrode material film within the region in which the other MISFET, e.g., the p-type MISFET, is to be formed is selectively removed, followed by forming a second gate electrode material film for the other MISFET, e.g., the p-type MISFET.
Suppose, for example, a hafnium nitride is used as the first gate electrode material for the n-type MISFET, and tungsten is used as the second gate electrode material for the p-type MISFET. In this case, the hafnium nitride layer formed in the p-type MISFET region is removed by a wet etching using, for example, a hydrogen peroxide solution, with a resist used as a mask.
However, in removing the gate electrode material such as hafnium nitride by the wet etching method, the gate insulating film in the region of forming the p-type MISFET is also exposed to the etching solution. In addition, the gate insulating film in the region of forming the p-type MISFET is also exposed to an organic solvent used for removing the resist. It follows that the dual metal gate process described above gives rise to a serious problem that the reliability of the gate insulating film of the p-type MISFET is markedly lowered.
Also, in order to make the n-type MISFET and the p-type MISFET different from each other in the work function of the gate electrode, disclosed is the technology of introducing an impurity into a tungsten silicide film by means of the ion implantation in, for example, Jpn. Pat. Aplln. KOKAI Publication No. 8-130216, Jpn. Pat. Aplln. KOKAI Publication No. 8-153804 and Jpn. Pat. Aplln. KOKAI Publication No. 9-246206. To be more specific, it is disclosed that an n-type impurity is introduced by the ion implantation into the tungsten silicide film of the n-type MISFET, and a p-type impurity is introduced by the ion implantation into the tungsten silicide film of the p-type MISFET so as to make the n-type MISFET and the p-type MISFET different from each other in the work function of the gate electrode.
However, since an impurity is introduced by the ion implantation into the tungsten silicide film, an additional problem is generated that the reliability of, for example, the gate insulating film is lowered because of the damage accompanying the ion implantation.
As described above, proposed is a dual metal gate process in which the gate electrode of the n-type MISFET is formed of a material differing in the work function from the material used for forming the gate electrode of the p-type MISFET. However, the dual metal gate process gives rise to the problem that the gate insulating film is exposed to the etching solution in removing the gate electrode material and to the solution used for removing the resist, with the result that the reliability of the gate insulating film is lowered. Also proposed is the technology that n-type and p-type impurities are introduced by the ion implantation into the silicide films so as to make the n-type MISFET and the p-type MISFET different from each other in the work function of the gate electrode. However, this technology gives rise to the problem that the reliability of, for example, the gate insulating film is lowered because of the damage accompanying the ion implantation. It follows that the characteristics and the reliability of the semiconductor device were likely to be lowered in the prior art.